It is often necessary to transmit multiple-bit signals from one sub-system in a computer system to another. For example, signals are frequently sent between a CPU and a device on a I/O bus. In a computer system with multiple clock domains, the source and destination sub-systems often run on different clocks. When multi-bit signals cross between unrelated clocking domains, there is a finite probability that the signals will not be sampled correctly. Specifically, the arrival time of each bit will be slightly different and the bit may or may not be sampled on the same clock edge in the destination sub-system. This leads to multi-bit values which are sampled incorrectly and faulty operation of the destination sub-system. For example, a two bit signal, 11, transmitted from a source sub-system operating at first clocking domain to a destination sub-system operating at a second clocking domain, at a current state of 00, may initially be sampled as one of four different states. Each of the bits may be sampled as a 0 or 1 independently, depending on the arrival time of the bit in the destination subsystem. Thus, a signal with binary values 00 changing to a value 11 may be sampled initially as 00, 01, or 10 before finally being resolved as 11. In situations when values 01 and 10 represent states with special meaning to circuitry in the destination sub-system, these transitional results would represent invalid data and could lead to faulty operation of the system.
One approach taken to sample multiple-bit signals correctly was the use of a qualifying signal. Data transmitted across asynchronous time domains were asserted for several clock periods by the transmitting sub-system until they were guaranteed to be sampled correctly by the receiving sub-system. After an appropriate number of clock periods, a qualifying signal was asserted by the transmitting sub-system to indicate to the receiving sub-system that the data is valid and ready to be sampled. The receiving sub-system sends an acknowledge signal back to the transmitting sub-system informing it which storage spaces are available for receiving additional data. Upon receiving the acknowledge signal, the transmitting sub-system asserts the next data. Typically, the time taken by the transmitting sub-system to generate a qualifying signal along with the time taken by the receiving sub-system to generate an acknowledge signal limits the amount of data that can be transmitted by the receiving sub-system during a given amount of time. In addition, the individual management required by each storage space involved implementation of additional hardware.
Another approach taken to sampling multi-bit signals was the use of phase-locked loops. Phase-locked loops operate to generate a clocking domain of a second sub-system from a clocking domain of a first sub-system. For example, a phase-locked loop can take a 66 MHz clock signal from a bus and multiply it by 1.5 to generate a 100 MHz internal clock signal for a CPU. The internal clock signal will thus be in a fixed phase relationship with the bus clock signal. Phase-locked loops guarantee phase alignment of the clock domains of two systems such that signals transmitted from the first sub-system may be sampled correctly by the second sub-system. There are, however, several drawbacks to the implementation of phase-locked loops. Phase-locked loops typically consume a large amount power to operate, require additional die area and significant hardware costs.
Thus, what is needed is a method and apparatus for sending multiple-bit signals between asynchronous clock domains. This method and apparatus should allow a high throughput of information between clocking domains and should be efficient and cost effective.